Operation | Parameter 1 | Parameter 2 | Parameter 3 | Description | Operator Number | Sample Instruction |
---|---|---|---|---|---|---|
add | destination register | source register | source register | Adds the values in the source registers and stores it in the destination register. | 10 | add $t0, $t1, $t2 |
sub | destination register | minuend register | subtrahend register | Subtracts the value in the subtrahend value from the minuend register and stores the result in the result register | Pseudo | sub $t0, $t1, $t2 |
or | destination register | source register | source register | Ors the values in the source registers and stores the result in the destination register | 14 | or $t0, $t1, $t2 |
ori | destination register | source register | 16 bit immediate value | Ors the value in the source register with the 16 bit immediate value | Pseudo | ori $t1, $t2, 0x16 |
neg | destination register | source register | N/A | Takes number stored in the source register and stores its 2's-compliment negation in the destination register. | 2 | neg $t0, $1 |
sll | destination register | source register | 4 bit immediate | Shifts the source register to the left by the immediate value then stores it in the destination register | 5 | sll $t0, $t1, 0x4 |
srl | destination register | source register | 4 bit immediate | Shifts the source register to the right by the immediate value then store the value in the destination register. | Pseudo | srl $t0, $t1, 0x4 |
lui | destination register | 8 bit immediate value | N/A | Loads the specified value into the upper 8 bits of a register without altering any other bits. | 3 | lui $t0, 0x12 |
lli | destination register | 8 bit immediate value | N/A | Loads the specified value into the lower 8 bits of a register without altering any other bits. | 4 | lli $t0, 0x34 |
li | destination register | 16 bit immediate value | N/A | Loads the immediate value into the destination register. | Pseudo | li $t0, 0x1234 |
lw | destination register | address register | 4 bit immediate value | Loads the value at the specified address plus offset from memory into the specified register. | 12 | lw $t0, 0x2($t1) |
la | destination register | Label | N/A | Load the address of the specified Label into the destination register. | Pseudo | la label |
sw | source register | address register | 4 bit immediate value | Store the value in the specified register to the specifed address in memory plus offset. | 13 | sw $t0, -0x2($t1) |
asp | general register | Write Flag | special register | Reads the value from the special purpose register into the general register if the write flag is set to zero or writes the value in the general purpose register into the special purpose register if the write flag is set to one. | 15 | asp $t0, 1 , $disp0 |
wrasp | general register | special register | N/A | Writes the value in the general purpose register into the specified special purpose register. | Pseudo | wrasp $t0, $disp0 |
reasp | general register | special register | N/A | Reads the value in the special purpose register into the specified general purpose register. | Pseduo | reasp $t0, $disp0 |
j | Label | N/A | N/A | Unconditionally jumps to the specified Label. | Pseudo | j label |
jsp | Label | N/A | N/A | Increments the stack pointer, stores the next execution address at the top of the stack, and jumps to the specified label. | Pseudo | jsp label |
rsp | N/A | N/A | N/A | Returns to the value at the top of the stack and decrements the stack pointer | Pseudo | rsp |
bne | source register | source register | jump register | If the source registers are not equal, then execution moves to the address specified in the jump register | 1 | bne $t0, $t1, $t2 |
bnel | source register | source register | Label | If the source registers are not equal, jump to the specified label. | Pseudo | ben $t0, $t1, label |
beq | source register | source register | jump register | If the source registers are equal, then continue execution at the address stored in the jump register | 0 | beq $t0, $t1, $t2 |
beql | source register | source register | Label | If the source registers are equal, jump to the specified label. | Pseudo | beq $t0, $t1, label |
slt | destination register | left source register | right source register | Sets the destination register to 1 if the left source register is less than than the right register or to 0 otherwise. | 8 | slt $t0, $t1, $t2 |
sgt | destination register | leff source register | right source register | Sets the destination register to 1 if the left source register is greater than then right source register or to 0 otherwise. | Pseudo | sgt $t0, $t1, $t2 |
rep | N/A | N/A | N/A | Moves execution back to the value stored in the exception program counter (presumably) after handling an exception. This also enables exception handling. | 11 | rep |
neg $as0, $t2 add $t0, $t1, $as0ori $t0, $t1, 0x00
lui $as0, 0x0 # Lower half of immediate value lli $as0, 0x0 # Upper half of immediate value or $t0, $t1, $as0srl $t0, $t1, 0x1
ssl $t0, $t1, 0x-1li $t0, 0x12
lui $as0, 0x1 lli $as0, 0x2 or $t0, $as0, $0la $t0, label
lui $as0, 0x0 # (First half of address computed by compiler) lli $as0, 0x0 # (Second half of address computed by compiler) or $t0, $as0, $0wrasp $t0, $disp0
asp $t0, 0, $disp0reasp $t0, $disp0
asp $t0, 1, $disp0jsp label
lui $as0, 0x0 # (First half of address computed by assembler) lli $as0, 0x0 # (Second half of address computer by assembler) add $sp, $sp, $1 add $sp, $sp, $1 or $as1, $0, $0 lli $as1, 0x6 asp $as2, 0, $pc add $as1, $as2, $as1 sw $as1, 0($sp) bne $0, $1, $as0rsp
neg $as0, $1 add $as0, $as0, $as0 add $sp, $sp, $as0 lw $as0, 2($sp) bne $0, $1, $as0j label
lui $as0, 0x0 # (First half of address computed by assembler) lli $as0, 0x0 # (Second half of address computer by assembler) bne $0, $1, $as0bnel $t0, $t1, label
lui $as0, 0x0 # (First half of address computed by assembler) lli $as0, 0x0 # (Second half of address computer by assembler) bne $t0, $t1, $as0beql $t0, $t1, label
lui $as0, 0x0 # (First half of address computed by assembler) lli $as0, 0x0 # (Second half of address computer by assembler) beq $t0, $t1, $as0sgt $t0, $t1, $t2
slt $t0, $t2, $t1
Example |
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Assembly Instruction: add $t0, $t1, $t2 Machine Instruction: 1010 0011 0100 0101 |
Assembly Instruction: lui $t0, 0x23 Machine Instruction: 0011 0011 0010 0011 |
Assembly Instruction: neg $t0, $t1 Machine Instruction: 0010 0011 0100 0000 |
Register Name | Register Number | Perferred Use |
---|---|---|
$zero | 0 | Always contains the value 0. Cannot be changed. |
$one | 1 | Always contains the value 1. Cannot be changed. |
$as0 | 2 | Reserved for assembler use |
$as1 | 3 | Reserved for assembler use |
$as2 | 4 | Reserved for assembler use |
$k0 | 5 | Reserved for kernal use |
$t0 | 6 | Volitile Storage |
$t1 | 7 | Volitile Storage |
$t2 | 8 | Volitile Storage |
$t3 | 9 | Volitile Storage |
$t4 | 10 | Volitile Storage |
$t5 | 11 | Volitile Storage |
$f0 | 12 | Storage space for arguments and return values from 'function' calls. |
$f1 | 13 | Storage space for arguments and return values from 'function' calls. |
$f2 | 14 | Storage space for arguments and return values from 'function' calls. |
$sp | 15 | The pointer to the top of the stack. |
Register Name | Register Number | Usage |
---|---|---|
$disp0 | 0 | Holds the value displayed onto the first LED Display |
$disp1 | 1 | Holds the value displayed onto the second LED Display |
$disp2 | 2 | Holds the value displayed onto the third LED Display |
$disp3 | 3 | Holds the value displayed onto the fourth LED Display |
4 | RESERVED | |
$sw0 | 5 | Holds the values of the switch input |
$pc | 6 | External view of the program counter. (Read-only) |
$epc | 7 | Stores the value of the PC before the last exception occured |
$irflag | 8 | Stores the a value which contains important information about the last interrupt that occured |
9 | RESERVED | |
$s00 | 10 | Storage which is consistent across function calls |
$s01 | 11 | Storage which is consistent across function calls |
$s02 | 12 | Storage which is consistent across function calls |
$s03 | 13 | Storage which is consistent across function calls |
$s04 | 14 | Storage which is consistent across function calls |
$s05 | 15 | Storage which is consistent across function calls |
$s06 | 16 | Storage which is consistent across function calls |
$s07 | 17 | Storage which is consistent across function calls |
$s08 | 18 | Storage which is consistent across function calls |
$s09 | 19 | Storage which is consistent across function calls |
$s10 | 20 | Storage which is consistent across function calls |
$s11 | 21 | Storage which is consistent across function calls |
$s12 | 22 | Storage which is consistent across function calls |
$s13 | 23 | Storage which is consistent across function calls |
$s14 | 24 | Storage which is consistent across function calls |
$s15 | 25 | Storage which is consistent across function calls |
$s16 | 26 | Storage which is consistent across function calls |
$s17 | 27 | Storage which is consistent across function calls |
$s18 | 28 | Storage which is consistent across function calls |
$s19 | 29 | Storage which is consistent across function calls |
$s20 | 30 | Storage which is consistent across function calls |
$s21 | 31 | Storage which is consistent across function calls |
$s22 | 32 | Storage which is consistent across function calls |
Cycle 0 | if(interruptOccured && interruptsEnabled) goto Interrupt Handler RTL |
||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Cycle 1 | IR = Mem[PC] PC = PC + 2 SPReg[7] = EPC | ||||||||||||||||
Cycle 2 | A = Reg[IR[11:8]] B = Reg[IR[7:4]] C = Reg[IR[3:0]] SPReg[6] = PC |
||||||||||||||||
if(IR[15:11] == 0) | if(IR[15:11] == 1) | if(IR[15:11] == 2) | if(IR[15:11] == 3) | if(IR[15:11] == 4) | if(IR[15:11] == 5) | if(IR[15:11] == 6) | if(IR[15:11] == 7) | if(IR[15:11] == 8) | if(IR[15:11] == 9) | if(IR[15:11] == 10) | if(IR[15:11] == 11) | if(IR[15:11] == 12) | if(IR[15:11] == 13) | if(IR[15:11] == 14) | if(IR[15:11] == 15) | ||
Cycle 3 | if(A == B) PC = C | if(A !=B ) PC = C | Sum = 0 - B | Reg[IR[11:8]] = IR[7:0] || A[7:0] | Reg[IR[11:8]] = A[15:8] || IR[7:0] | Reg[IR[11:8]] = B << SE[IR[3:0]] | if(B < C) Reg[IR[11:8]] = 1 else Reg[IR[11:8]] = 0 | Sum = B + C | PC = EPC interruptsEnabled = 1 | Sum = B + SE[IR[3..0]] | Sum = B + SE[IR[3..0]] | OROUT = B | C | if(IR[10] == 1) SPReg[IR[5:0]] = A | if(IR[10] == 0) Reg[IR[11:8]] = SPReg[IR[5:0]] | |||
Cycle 4 | Reg[IR[11:8]] = Sum | Reg[IR[11:8]] = Sum | MDR = Mem[Sum] | Mem[Sum] = A | Reg[IR[11:8]] = OROUT | ||||||||||||
Cycle 5 | Reg[IR[11:8]] = MDR |
Cycle 0.5 | EPC = PC PC = Reg[5] SPReg[8] = interruptFlag interruptsEnabled = 0 |
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16-bit Flag | ||
3-bit type | 7-bit reserved | 6-bit value |
= | is an assignment operator |
| | is a bitwise OR |
< | is true iff the left operator is less than the right operator |
<< | is a left bit shift |
|| | is a bitwise concatenation |
!= | is a bitwise Not Equal |
== | is a bitwise Equal |
Value[num1:num2] | are the bits between num1 and num2 (inclusive) in Value |
if(condition) | continues execution of the instruction if condition is true |
SE[Value] | extends value to a 16-bit number which represents the same value as Value |
Mem[Value] | is a location in memory |
Reg[Value] | is a specific general purpose register |
SPReg[Value] | is a specific special purpose register |
Component | Inputs | Outputs | Control Signals | Notes |
---|---|---|---|---|
Adder | Input115:0 Input215:0 | Output15:0 | SubtractEnable | Adds the two inputs and returns the sum in the output. |
Comparator | Input115:0 Input215:0 | Output0:0 | Output is high iff the two Inputs are identical. | |
LTEngine | Input115:0 Input215:0 | Output0:0 | Output is high iff Input1 is less than Input2 when interpreted as 2's complement integers. | |
Shifter | Input115:0 Input215:0 | Output15:0 | Bit Shifts Input1 by the amount specified in Input2 (which is interpreted as a 2's complement integer). | |
IR | IRIn15:0 | IROut15:0 | IRWrite | Stores the current instruction. |
PC | PCIn15:0 | PCOut15:0 | PCWrite | Stores the value of the next memory address to be executed. |
EPC | EPCIn15:0 | EPCOut15:0 | EPCWrite | Stores the value of the next memory address to be execution after completion of exception handling. |
A | AIn15:0 | AOut15:0 | Temporary Storage | |
B | BIn15:0 | BOut15:0 | Temporary Storage | |
C | CIn15:0 | COut15:0 | Temporary Storage | |
Sum | Input15:0 | Output15:0 | Stores the output from addition and subtraction operations | |
MDR | Input15:0 | Output15:0 | Stores the output from memory read operations | |
OROUT | Input15:0 | Output15:0 | Stores the output from bitwise OR operations | |
SE4 | Input3:0 | Output15:0 | Takes the 4 bit input and replicates the most significant bit until it is 16 bits long. | |
SE12 | Input11:0 | Output15:0 | Takes the 12 bit input and replicates the most significant bit until it is 16 bits long. | |
Reg | ReadReg13:0 ReadReg23:0 ReadReg33:0 WriteReg3:0 WriteValue15:0 | ReadOut115:0 ReadOut215:0 ReadOut315:0 | WriteEnable | Reads the values registers which correspond to the values in the ReadReg registers. Can also write a specified value to the register specified in WriteReg iff the WriteEnable flag is set. |
SPReg | ReadReg3:0 WriteReg3:0 WriteValue15:0 | ReadValue15:0 | WriteEnable | Read values from special purpose registers. Can also write the value in WriteValue to to the specified special purpose register when the WriteEnable flag is set. |
Mem | ReadAddress15:0 WriteAddress15:0 WriteValue15:0 | ReadValue15:0 | WriteEnable | Reads the value from the specified address in memory. Can also write the specified value to an address in memory if the WriteEnable flag is set. |
Control Unit | Opcode3:0 ComparatorOutput0:0 ASPWriteFlag0:0 LTEngineOutput0:0 | Control Flow | Controls operation flow | |
Concatenator | Input17:0 Input27:0 | Output15:0 | Takes the 8 bits in Input1 and appends the eight bits in Input2. |
Control Signal | Description | Bit Width |
---|---|---|
Outputs | ||
EPCWEn | This control signal is set to high to allow a value to be written to the EPC | 1 |
PCWEn | This control signal is set to high to allow a value to be written to the PC | 1 |
SPRegWEn | This control signal is set to high to allow a value to be written to the SPRegister File | 1 |
MemWEn | This control signal is set to high to allow a value to be written to Memory | 1 |
AWEn | This control signal is set to high to allow a value to be written to the register A | 1 |
BWEn | This control signal is set to high to allow a value to be written to the register B | 1 |
CWEn | This control signal is set to high to allow a value to be written to the register C | 1 |
RegWEn | This control signal is set to high to allow a value to be written to the Register File | 1 |
IRWEn | This control signal is set to high to allow a value to be written to the register IR | 1 |
IFEn | This control signal is set to high to allow a value to be written to the Interrupt Flag | 1 |
PCInputSelect | This control signal determines what value will be written to the PC | 2 |
SPRegisterWriteSource | This control signal determines what value will be written to the SPRegister file | 2 |
MemoryReadAddressSelect | This control signal determines which memory address to read from | 2 |
AdderInputSelect | This control signal determines which values will be passed into the adder | 2 |
Subtract | This control signal determines whether the adder adds the two inputs together (if the signal is low), or subtracts them(if the signal is high) | 1 |
RegisterReadMode | This control signal is high in order to read the address of the exception handling routine. | 1 |
RegisterWriteDataSourceSelect | This control signal determines which value to write to the Register File | 3 |
InterruptFlag | This control signal determines whether or not an interrupt has occured | 16 |
Inputs | ||
Comparator Result | This is inputted into the control signal to determine if a jump should occur | 1 |
Instruction | This is inputted into the control signal because it is the opcode of the instructions, therefore it dictates what the processor needs to do | 4 |
InstMod | This bit is used in order to determine if the processor needs to read from or write to the SPRegister File | 1 |
Test Number | Procedure |
---|---|
1-00 | Multiplexers (All): We will test all our multiplexers by giving each pin a unique but static value and manipulating the control signal manually to ensure that the correct values are being sent to the output. |
1-01 | Or: We will set each pin to a static 16-bit signed value and check the output to verify that the two inputs have had the bitwise Or operation applied to them. We will test this at least three times with different values to verify correct implementation. |
1-02 | The adder will accept two 16-bit signed integer inputs and output a 16-bit signed integer input. We will test this by tying the inputs to specific test values to observe the output. At this time, overflow handling exceptions for the adder are not being considered. |
1-03 | The comparator accepts two 16-bit signed integers and compares the two values to see if they are equal. We will test this by using at least four different sets of pre-determined values (two equal, two not equal) to make sure that the comparator outputs a 1 if the two values are equal and 0 if the two values are not equal. |
1-04 | We will test the LTEngine (Less-than engine) by assigning pre-determined values to the Bout and Cout pins to ensure that a 1 is the result of Bout < Cout, and a 0 is a result of Bout <> Cout. We will test this six times with different values, two cases with Bout < Cout, two cases with Bout > Cout, and two cases with Bout = Cout. |
1-05 | PC/EPC/InterruptFlag/A/B/C/IR registers will be tested by inputting a value to the register making sure that the values in the flip-flops are preserved until the reset condition (Clk is a positive edge) is met. We will verify results by testing each register twice. |
1-06 | The register will be tested with the values of the pins assigned to arbitrary values. The control signals will be varied to ensure that the registers are having data properly written to them and output. We will test each register address twice. |
1-07 | The concatenater will be assigned two 8-bit signed values and we will verify that the output is the value of Input1 with Input2 concatenated on the end. We will test the concatenater with two different values for Input 1 and Input2. |
1-08 | The variable shifter will be assigned a 16-bit value and a shift amount, and we will verify that the output is the input left-shifted by the shift amount and represented as a 2s complement integer. We will test the shifter four times, including two right-shift tests, where the shift amount is a negative value of a left shift input. |
1-09 | The SPregister unit will be tested in a similar fashion to the register unit. Values will be manually assigned to pins, and control signals will be manually manipulated to ensure that values are properly being written to and read from their respective locations. Each address will be tested twice. |
1-10 | The memory will be tested in a similar fashion to the SPregister and register units. Values will be assigned to pins and clock signals will be manually manipulated to verify that the memory is able to store and output values correctly. |
1-11 | The control unit will be given arbitrary values corresponding to our instructions to verify that the proper control signals are set high or low. Each instruction will be tested twice to make sure the proper control signals are set correctly. |