Design Document


This document outlines the design and implementation of the Mach 5 Proccessor Architecture. The Mach 5 architecture is a 16-bit architecture. Each instruction is fixed width at 16 bits. There are 16 addressable instructions and 16 addressable general purpose registers. There are also 32 special purpose registers, some of these registers are availible for use while others have a predefined purpose.

Table of Contents

  1. Assembly Language Specification
  2. Implementations of Pseudo Instructions
  3. Machine Language Specification
  4. Register Specification
  5. Register Transfer Language Specification
  6. RTL Test Plan
  7. Componenets List
  8. Datapath
  9. Control Signals
  10. Unit Test Plan
  11. Integration Plan
  12. Sample Programs

Assembly Language Specification:

OperationParameter 1Parameter 2Parameter 3DescriptionOperator NumberSample Instruction
Mathematical Operations
adddestination registersource registersource registerAdds the values in the source registers and stores it in the destination register.10add $t0, $t1, $t2
subdestination registerminuend registersubtrahend registerSubtracts the value in the subtrahend value from the minuend register and stores the result in the result registerPseudosub $t0, $t1, $t2
ordestination registersource registersource registerOrs the values in the source registers and stores the result in the destination register14or $t0, $t1, $t2
oridestination registersource register16 bit immediate valueOrs the value in the source register with the 16 bit immediate valuePseudoori $t1, $t2, 0x16
negdestination registersource registerN/ATakes number stored in the source register and stores its 2's-compliment negation in the destination register.2neg $t0, $1
Shift Operations
slldestination registersource register4 bit immediateShifts the source register to the left by the immediate value then stores it in the destination register5sll $t0, $t1, 0x4
srldestination registersource register4 bit immediateShifts the source register to the right by the immediate value then store the value in the destination register.Pseudosrl $t0, $t1, 0x4
Register Manipulation/Memory Instructions
luidestination register8 bit immediate valueN/ALoads the specified value into the upper 8 bits of a register without altering any other bits.3lui $t0, 0x12
llidestination register8 bit immediate valueN/ALoads the specified value into the lower 8 bits of a register without altering any other bits.4lli $t0, 0x34
lidestination register16 bit immediate valueN/ALoads the immediate value into the destination register.Pseudoli $t0, 0x1234
lwdestination registeraddress register4 bit immediate valueLoads the value at the specified address plus offset from memory into the specified register.12lw $t0, 0x2($t1)
ladestination registerLabelN/ALoad the address of the specified Label into the destination register.Pseudola label
swsource registeraddress register4 bit immediate valueStore the value in the specified register to the specifed address in memory plus offset.13sw $t0, -0x2($t1)
aspgeneral registerWrite Flagspecial registerReads the value from the special purpose register into the general register if the write flag is set to zero or writes the value in the general purpose register into the special purpose register if the write flag is set to one.15asp $t0, 1 , $disp0
wraspgeneral registerspecial registerN/AWrites the value in the general purpose register into the specified special purpose register.Pseudowrasp $t0, $disp0
reaspgeneral registerspecial registerN/AReads the value in the special purpose register into the specified general purpose register.Pseduoreasp $t0, $disp0
Branch Instructions
jLabelN/AN/AUnconditionally jumps to the specified Label.Pseudoj label
jspLabelN/AN/AIncrements the stack pointer, stores the next execution address at the top of the stack, and jumps to the specified label.Pseudojsp label
rspN/AN/AN/AReturns to the value at the top of the stack and decrements the stack pointerPseudorsp
bnesource registersource registerjump registerIf the source registers are not equal, then execution moves to the address specified in the jump register1bne $t0, $t1, $t2
bnelsource registersource registerLabelIf the source registers are not equal, jump to the specified label.Pseudoben $t0, $t1, label
beqsource registersource registerjump registerIf the source registers are equal, then continue execution at the address stored in the jump register0beq $t0, $t1, $t2
beqlsource registersource registerLabelIf the source registers are equal, jump to the specified label.Pseudobeq $t0, $t1, label
Logical Instructions
sltdestination registerleft source registerright source registerSets the destination register to 1 if the left source register is less than than the right register or to 0 otherwise.8slt $t0, $t1, $t2
sgtdestination registerleff source registerright source registerSets the destination register to 1 if the left source register is greater than then right source register or to 0 otherwise.Pseudosgt $t0, $t1, $t2
Exception Handling Instructions
repN/AN/AN/AMoves execution back to the value stored in the exception program counter (presumably) after handling an exception. This also enables exception handling.11rep
Notes: All opcodes are represented in machine code as 4-bit numbers. All general registers are represented as 4-bit numbers. Special registers are 6-bits in length. The write flag specified in asp is 1 bit. Unless otherwise specifed, all 'source' and 'destination' registers are general registers.

Pseudo Instruction Implementations

sub $t0, $t1, $t2
 neg $as0, $t2
 add $t0, $t1, $as0
 
ori $t0, $t1, 0x00
 lui $as0, 0x0  # Lower half of immediate value
 lli $as0, 0x0  # Upper half of immediate value
 or  $t0, $t1, $as0
 
srl $t0, $t1, 0x1
 ssl $t0, $t1, 0x-1
 
li $t0, 0x12
 lui $as0, 0x1
 lli $as0, 0x2
 or $t0, $as0, $0
 
la $t0, label
 lui $as0, 0x0	# (First half of address computed by compiler)
 lli $as0, 0x0  # (Second half of address computed by compiler)
 or $t0, $as0, $0
 
wrasp $t0, $disp0
 asp $t0, 0, $disp0
 
reasp $t0, $disp0
 asp $t0, 1, $disp0
 
jsp label
 lui $as0, 0x0 # (First half of address computed by assembler)
 lli $as0, 0x0 # (Second half of address computer by assembler)
 add $sp, $sp, $1
 add $sp, $sp, $1
 or $as1, $0, $0
 lli $as1, 0x6
 asp $as2, 0, $pc
 add $as1, $as2, $as1
 sw $as1, 0($sp)
 bne $0, $1, $as0
 
rsp
 neg $as0, $1
 add $as0, $as0, $as0
 add $sp, $sp, $as0
 lw $as0, 2($sp)
 bne $0, $1, $as0
 
j label
 lui $as0, 0x0 # (First half of address computed by assembler)
 lli $as0, 0x0 # (Second half of address computer by assembler)
 bne $0, $1, $as0
 
bnel $t0, $t1, label
 lui $as0, 0x0 # (First half of address computed by assembler)
 lli $as0, 0x0 # (Second half of address computer by assembler)
 bne $t0, $t1, $as0
 
beql $t0, $t1, label
 
 lui $as0, 0x0 # (First half of address computed by assembler)  
 lli $as0, 0x0 # (Second half of address computer by assembler)   
 beq $t0, $t1, $as0    
 
sgt $t0, $t1, $t2
 slt $t0, $t2, $t1
 


Machine Language Specification:


When designing an assembler for the Mach 5 architecture, the translation of assembly language instructions into machine code is straightforward. Each non-pseudo instruction is 16 bits wide. The first 4 bits of this number are the "Operation number" which is specified in the table above. The remaining 14 bits are the parameters, listed in the same order as above.

Example

 Assembly Instruction:	add	$t0, $t1, $t2
 Machine  Instruction:  1010 0011 0100 0101 
 

 Assembly Instruction:	lui	$t0, 0x23
 Machine  Instruction:  0011 0011 0010 0011
 

 Assembly Instruction:  neg     $t0, $t1
 Machine  Instruction:  0010 0011 0100 0000 
 


Register Specification:

General Purpose

Register NameRegister NumberPerferred Use
$zero0Always contains the value 0. Cannot be changed.
$one1Always contains the value 1. Cannot be changed.
$as02Reserved for assembler use
$as13Reserved for assembler use
$as24Reserved for assembler use
$k05Reserved for kernal use
$t06Volitile Storage
$t17Volitile Storage
$t28Volitile Storage
$t39Volitile Storage
$t410Volitile Storage
$t511Volitile Storage
$f012Storage space for arguments and return values from 'function' calls.
$f113Storage space for arguments and return values from 'function' calls.
$f214Storage space for arguments and return values from 'function' calls.
$sp15The pointer to the top of the stack.

Special Purpose

Register NameRegister NumberUsage
$disp00Holds the value displayed onto the first LED Display
$disp11Holds the value displayed onto the second LED Display
$disp22Holds the value displayed onto the third LED Display
$disp33Holds the value displayed onto the fourth LED Display
 4RESERVED
$sw05Holds the values of the switch input
$pc6External view of the program counter. (Read-only)
$epc7Stores the value of the PC before the last exception occured
$irflag8Stores the a value which contains important information about the last interrupt that occured
 9RESERVED
$s0010Storage which is consistent across function calls
$s0111Storage which is consistent across function calls
$s0212Storage which is consistent across function calls
$s0313Storage which is consistent across function calls
$s0414Storage which is consistent across function calls
$s0515Storage which is consistent across function calls
$s0616Storage which is consistent across function calls
$s0717Storage which is consistent across function calls
$s0818Storage which is consistent across function calls
$s0919Storage which is consistent across function calls
$s1020Storage which is consistent across function calls
$s1121Storage which is consistent across function calls
$s1222Storage which is consistent across function calls
$s1323Storage which is consistent across function calls
$s1424Storage which is consistent across function calls
$s1525Storage which is consistent across function calls
$s1626Storage which is consistent across function calls
$s1727Storage which is consistent across function calls
$s1828Storage which is consistent across function calls
$s1929Storage which is consistent across function calls
$s2030Storage which is consistent across function calls
$s2131Storage which is consistent across function calls
$s2232Storage which is consistent across function calls


Register Transfer Language Specification

Cycle 0if(interruptOccured && interruptsEnabled)
goto Interrupt Handler RTL
Cycle 1IR = Mem[PC]
PC = PC + 2
SPReg[7] = EPC
Cycle 2A = Reg[IR[11:8]]
B = Reg[IR[7:4]]
C = Reg[IR[3:0]]
SPReg[6] = PC
if(IR[15:11] == 0) if(IR[15:11] == 1)if(IR[15:11] == 2)if(IR[15:11] == 3)if(IR[15:11] == 4)if(IR[15:11] == 5)if(IR[15:11] == 6)if(IR[15:11] == 7)if(IR[15:11] == 8)if(IR[15:11] == 9)if(IR[15:11] == 10)if(IR[15:11] == 11)if(IR[15:11] == 12)if(IR[15:11] == 13)if(IR[15:11] == 14)if(IR[15:11] == 15)
Cycle 3if(A == B)
PC = C
if(A !=B )
PC = C
Sum = 0 - BReg[IR[11:8]] = IR[7:0] || A[7:0]Reg[IR[11:8]] = A[15:8] || IR[7:0] Reg[IR[11:8]] = B << SE[IR[3:0]]if(B < C)
Reg[IR[11:8]] = 1
else
Reg[IR[11:8]] = 0
 Sum = B + CPC = EPC
interruptsEnabled = 1
Sum = B + SE[IR[3..0]]Sum = B + SE[IR[3..0]]OROUT = B | Cif(IR[10] == 1)
SPReg[IR[5:0]] = A
if(IR[10] == 0)
Reg[IR[11:8]] = SPReg[IR[5:0]]
Cycle 4Reg[IR[11:8]] = SumReg[IR[11:8]] = SumMDR = Mem[Sum]Mem[Sum] = AReg[IR[11:8]] = OROUT
Cycle 5Reg[IR[11:8]] = MDR

Interrupt Handler RTL

Cycle 0.5EPC = PC
PC = Reg[5]
SPReg[8] = interruptFlag
interruptsEnabled = 0

Interrupt Flag Format

16-bit Flag
3-bit type7-bit reserved6-bit value
Type is either 1 (for interrupt) or 2 (for exception).
The reserved value is set to zero.
Value is either the id of the device which caused the interrupt or the exception number.

Assumptions about RTL:

=is an assignment operator
|is a bitwise OR
<is true iff the left operator is less than the right operator
<< is a left bit shift
||is a bitwise concatenation
!=is a bitwise Not Equal
== is a bitwise Equal
Value[num1:num2] are the bits between num1 and num2 (inclusive) in Value
if(condition) continues execution of the instruction if condition is true
SE[Value] extends value to a 16-bit number which represents the same value as Value
Mem[Value] is a location in memory
Reg[Value] is a specific general purpose register
SPReg[Value] is a specific special purpose register


RTL Test Plan



Components List


ComponentInputsOutputsControl SignalsNotes
Operational Units
AdderInput115:0
Input215:0
Output15:0SubtractEnableAdds the two inputs and returns the sum in the output.
ComparatorInput115:0
Input215:0
Output0:0Output is high iff the two Inputs are identical.
LTEngineInput115:0
Input215:0
Output0:0Output is high iff Input1 is less than Input2 when interpreted as 2's complement integers.
ShifterInput115:0
Input215:0
Output15:0Bit Shifts Input1 by the amount specified in Input2 (which is interpreted as a 2's complement integer).
Single Word Storage
IRIRIn15:0IROut15:0IRWriteStores the current instruction.
PCPCIn15:0PCOut15:0PCWriteStores the value of the next memory address to be executed.
EPCEPCIn15:0EPCOut15:0EPCWriteStores the value of the next memory address to be execution after completion of exception handling.
AAIn15:0AOut15:0Temporary Storage
BBIn15:0BOut15:0Temporary Storage
CCIn15:0COut15:0Temporary Storage
SumInput15:0Output15:0Stores the output from addition and subtraction operations
MDRInput15:0Output15:0Stores the output from memory read operations
OROUTInput15:0Output15:0Stores the output from bitwise OR operations
Sign Extension Units
SE4Input3:0Output15:0Takes the 4 bit input and replicates the most significant bit until it is 16 bits long.
SE12Input11:0Output15:0Takes the 12 bit input and replicates the most significant bit until it is 16 bits long.
Distant Storage
RegReadReg13:0
ReadReg23:0
ReadReg33:0
WriteReg3:0
WriteValue15:0
ReadOut115:0
ReadOut215:0
ReadOut315:0
WriteEnableReads the values registers which correspond to the values in the ReadReg registers. Can also write a specified value to the register specified in WriteReg iff the WriteEnable flag is set.
SPRegReadReg3:0
WriteReg3:0
WriteValue15:0
ReadValue15:0WriteEnableRead values from special purpose registers. Can also write the value in WriteValue to to the specified special purpose register when the WriteEnable flag is set.
MemReadAddress15:0
WriteAddress15:0
WriteValue15:0
ReadValue15:0WriteEnableReads the value from the specified address in memory. Can also write the specified value to an address in memory if the WriteEnable flag is set.
Other
Control UnitOpcode3:0
ComparatorOutput0:0
ASPWriteFlag0:0
LTEngineOutput0:0
Control FlowControls operation flow
ConcatenatorInput17:0
Input27:0
Output15:0Takes the 8 bits in Input1 and appends the eight bits in Input2.


Datapath

Datapath

Control Signals

Control SignalDescriptionBit Width
Outputs
EPCWEn This control signal is set to high to allow a value to be written to the EPC 1
PCWEn This control signal is set to high to allow a value to be written to the PC 1
SPRegWEn This control signal is set to high to allow a value to be written to the SPRegister File 1
MemWEn This control signal is set to high to allow a value to be written to Memory 1
AWEn This control signal is set to high to allow a value to be written to the register A 1
BWEn This control signal is set to high to allow a value to be written to the register B 1
CWEn This control signal is set to high to allow a value to be written to the register C 1
RegWEn This control signal is set to high to allow a value to be written to the Register File 1
IRWEn This control signal is set to high to allow a value to be written to the register IR 1
IFEn This control signal is set to high to allow a value to be written to the Interrupt Flag 1
PCInputSelect This control signal determines what value will be written to the PC 2
SPRegisterWriteSource This control signal determines what value will be written to the SPRegister file 2
MemoryReadAddressSelect This control signal determines which memory address to read from 2
AdderInputSelect This control signal determines which values will be passed into the adder 2
Subtract This control signal determines whether the adder adds the two inputs together (if the signal is low), or subtracts them(if the signal is high) 1
RegisterReadMode This control signal is high in order to read the address of the exception handling routine. 1
RegisterWriteDataSourceSelect This control signal determines which value to write to the Register File 3
InterruptFlag This control signal determines whether or not an interrupt has occured 16
Inputs
Comparator Result This is inputted into the control signal to determine if a jump should occur 1
Instruction This is inputted into the control signal because it is the opcode of the instructions, therefore it dictates what the processor needs to do 4
InstMod This bit is used in order to determine if the processor needs to read from or write to the SPRegister File 1


Unit Test Plan

All testing will be done by inserting the component under inspection into a separate schematic file for testing.
Test NumberProcedure
1-00Multiplexers (All): We will test all our multiplexers by giving each pin a unique but static value and manipulating the control signal manually to ensure that the correct values are being sent to the output.
1-01Or: We will set each pin to a static 16-bit signed value and check the output to verify that the two inputs have had the bitwise Or operation applied to them. We will test this at least three times with different values to verify correct implementation.
1-02The adder will accept two 16-bit signed integer inputs and output a 16-bit signed integer input. We will test this by tying the inputs to specific test values to observe the output. At this time, overflow handling exceptions for the adder are not being considered.
1-03The comparator accepts two 16-bit signed integers and compares the two values to see if they are equal. We will test this by using at least four different sets of pre-determined values (two equal, two not equal) to make sure that the comparator outputs a 1 if the two values are equal and 0 if the two values are not equal.
1-04We will test the LTEngine (Less-than engine) by assigning pre-determined values to the Bout and Cout pins to ensure that a 1 is the result of Bout < Cout, and a 0 is a result of Bout <> Cout. We will test this six times with different values, two cases with Bout < Cout, two cases with Bout > Cout, and two cases with Bout = Cout.
1-05PC/EPC/InterruptFlag/A/B/C/IR registers will be tested by inputting a value to the register making sure that the values in the flip-flops are preserved until the reset condition (Clk is a positive edge) is met. We will verify results by testing each register twice.
1-06The register will be tested with the values of the pins assigned to arbitrary values. The control signals will be varied to ensure that the registers are having data properly written to them and output. We will test each register address twice.
1-07The concatenater will be assigned two 8-bit signed values and we will verify that the output is the value of Input1 with Input2 concatenated on the end. We will test the concatenater with two different values for Input 1 and Input2.
1-08The variable shifter will be assigned a 16-bit value and a shift amount, and we will verify that the output is the input left-shifted by the shift amount and represented as a 2s complement integer. We will test the shifter four times, including two right-shift tests, where the shift amount is a negative value of a left shift input.
1-09The SPregister unit will be tested in a similar fashion to the register unit. Values will be manually assigned to pins, and control signals will be manually manipulated to ensure that values are properly being written to and read from their respective locations. Each address will be tested twice.
1-10The memory will be tested in a similar fashion to the SPregister and register units. Values will be assigned to pins and clock signals will be manually manipulated to verify that the memory is able to store and output values correctly.
1-11The control unit will be given arbitrary values corresponding to our instructions to verify that the proper control signals are set high or low. Each instruction will be tested twice to make sure the proper control signals are set correctly.


Integration Test Plan

In order to expedite the process of finishing the next milestone, we decided to use Xilinx to draw our datapath layout (accessible here) according to our RTL description. For this reason, or integration test plan will focus on the order in which the parts are programmed, rather than the order in which parts are added into the current design. For this reason, our integration test plan will proceed accordingly:
  1. We will implement our Multiplexers and test them first (Unit Test Plan 1-0)
  2. We will implement our Or gate and test it (Unit Test Plan 1-1)
  3. We will implement the adder first and test it (Unit Test Plan 1-2)
  4. We will implement our comparator and test it (Unit Test Plan 1-3)
  5. We will implement and test our LTEngine (Unit Test Plan 1-4)
  6. We will implement and test our PC, EPC, InterruptFlag, A, B, C, and IR registers and test them (Unit Test Plan 1-5). We will verify that the A, B, and C registers properly interface with the adder, comparator, LTEnginer and corresponding multiplexers.
  7. We will implement our register unit and test it (Unit Test Plan 1-6). In addition, we will test to ensure that the register is properly able to send values to the A, B, and C registers while verifying that these registers are still properly cooperating with the adder, comparator, and LTEngine
  8. The concatenator will then be implemented and tested (Unit Test Plan 1-7).
  9. We will implement and test our variable shifter (Unit Test Plan 1-8).
  10. We will implement and test our SPregister unit (Unit Test Plan 1-9).
  11. We will implement and test our memory unit (Unit Test Plan 1-10). We will verify that a value at a location in memory is able to be read into a register, and a value from a register is able to be written to memory.
  12. We will verify that each component is properly sending output to the correct destination.
  13. Lastly, we will implement and test our control unit (Unit Test Plan 1-11).
  14. We will verify that the control unit is able to autonomously control the circuit and cycle through instructions to perform the desired action.

Sample Programs:

Euclid's Algorithm binary
Volume of a Rectangular Prism binary