Design Document

This document outlines the design and implementation of the Mach 5 Proccessor Architecture. The Mach 5 architecture is a 16-bit architecture. Each instruction is fixed width at 16 bits. There are 16 addressable instructions and 16 addressable general purpose registers. There are also 32 special purpose registers, some of these registers are availible for use while others have a predefined purpose.

Assembly Language Specification:

Operation	Parameter 1	Parameter 2	Parameter 3	Description	Operator Number	Sample Instruction
Mathematical Operations
add	destination register	source register	source register	Adds the values in the source registers and stores it in the destination register.	10	add $t0, $t1, $t2
sub	destination register	minuend register	subtrahend register	Subtracts the value in the subtrahend value from the minuend register and stores the result in the result register	Pseudo	sub $t0, $t1, $t2
or	destination register	source register	source register	Ors the values in the source registers and stores the result in the destination register	14	or $t0, $t1, $t2
ori	destination register	source register	16 bit immediate value	Ors the value in the source register with the 16 bit immediate value	Pseudo	ori $t1, $t2, 0x16
neg	destination register	source register	N/A	Takes number stored in the source register and stores its 2's-compliment negation in the destination register.	2	neg $t0, $1
Shift Operations
sll	destination register	source register	4 bit immediate	Shifts the source register to the left by the immediate value then stores it in the destination register	5	sll $t0, $t1, 0x4
srl	destination register	source register	4 bit immediate	Shifts the source register to the right by the immediate value then store the value in the destination register.	Pseudo	srl $t0, $t1, 0x4
Register Manipulation/Memory Instructions
lui	destination register	8 bit immediate value	N/A	Loads the specified value into the upper 8 bits of a register without altering any other bits.	3	lui $t0, 0x12
lli	destination register	8 bit immediate value	N/A	Loads the specified value into the lower 8 bits of a register without altering any other bits.	4	lli $t0, 0x34
li	destination register	16 bit immediate value	N/A	Loads the immediate value into the destination register.	Pseudo	li $t0, 0x1234
lw	destination register	address register	4 bit immediate value	Loads the value at the specified address plus offset from memory into the specified register.	12	lw $t0, 0x2($t1)
la	destination register	Label	N/A	Load the address of the specified Label into the destination register.	Pseudo	la label
sw	source register	address register	4 bit immediate value	Store the value in the specified register to the specifed address in memory plus offset.	13	sw $t0, -0x2($t1)
asp	general register	Write Flag	special register	Reads the value from the special purpose register into the general register if the write flag is set to zero or writes the value in the general purpose register into the special purpose register if the write flag is set to one.	15	asp $t0, 1 , $disp0
wrasp	general register	special register	N/A	Writes the value in the general purpose register into the specified special purpose register.	Pseudo	wrasp $t0, $disp0
reasp	general register	special register	N/A	Reads the value in the special purpose register into the specified general purpose register.	Pseduo	reasp $t0, $disp0
Branch Instructions
j	Label	N/A	N/A	Unconditionally jumps to the specified Label.	Pseudo	j label
jsp	Label	N/A	N/A	Increments the stack pointer, stores the next execution address at the top of the stack, and jumps to the specified label.	Pseudo	jsp label
rsp	N/A	N/A	N/A	Returns to the value at the top of the stack and decrements the stack pointer	Pseudo	rsp
bne	source register	source register	jump register	If the source registers are not equal, then execution moves to the address specified in the jump register	1	bne $t0, $t1, $t2
bnel	source register	source register	Label	If the source registers are not equal, jump to the specified label.	Pseudo	ben $t0, $t1, label
beq	source register	source register	jump register	If the source registers are equal, then continue execution at the address stored in the jump register	0	beq $t0, $t1, $t2
beql	source register	source register	Label	If the source registers are equal, jump to the specified label.	Pseudo	beq $t0, $t1, label
Logical Instructions
slt	destination register	left source register	right source register	Sets the destination register to 1 if the left source register is less than than the right register or to 0 otherwise.	8	slt $t0, $t1, $t2
sgt	destination register	leff source register	right source register	Sets the destination register to 1 if the left source register is greater than then right source register or to 0 otherwise.	Pseudo	sgt $t0, $t1, $t2
Exception Handling Instructions
jep	12-bit address offset	N/A	N/A	Moves execution to the exception handling code and stores a copy of the current value in the program counter to the exception program counter	9	jep
rep	N/A	N/A	N/A	Moves execution back to the value stored in the exception program counter (presumably) after handling an exception.	11	rep

Notes: All opcodes are represented in machine code as 4-bit numbers. All general registers are represented as 4-bit numbers. Special registers are 7-bits in length. The write flag specified in asp is 1 bit. Unless otherwise specifed, all 'source' and 'destination' registers are general registers.

Pseudo Instruction Implementations

sub $t0, $t1, $t2

 neg $as0, $t2
 add $t0, $t1, $as0

ori $t0, $t1, 0x00

 lui $as0, 0x0  # Lower half of immediate value
 lli $as0, 0x0  # Upper half of immediate value
 or  $t0, $t1, $as0

srl $t0, $t1, 0x1

 ssl $t0, $t1, 0x-1

li $t0, 0x12

 lui $as0, 0x1
 lli $as0, 0x2
 or $t0, $as0, $0

la $t0, label

 lui $as0, 0x0	# (First half of address computed by compiler)
 lli $as0, 0x0  # (Second half of address computed by compiler)
 or $t0, $as0, $0

wrasp $t0, $disp0

 asp $t0, 0, $disp0

reasp $t0, $disp0

 asp $t0, 1, $disp0

jsp label

 lui $as0, 0x0 # (First half of address computed by assembler)
 lli $as0, 0x0 # (Second half of address computer by assembler)
 add $sp, $sp, $1
 add $sp, $sp, $1
 or $as1, $0, $0
 lli $as1, 0x6
 asp $as2, 0, $pc
 add $as1, $as2, $as1
 sw $as1, 0($sp)
 bne $0, $1, $as0

rsp

 neg $as0, $1
 add $as0, $as0, $as0
 add $sp, $sp, $as0
 lw $as0, 2($sp)
 bne $0, $1, $as0

j label

 lui $as0, 0x0 # (First half of address computed by assembler)
 lli $as0, 0x0 # (Second half of address computer by assembler)
 bne $0, $1, $as0

bnel $t0, $t1, label

 lui $as0, 0x0 # (First half of address computed by assembler)
 lli $as0, 0x0 # (Second half of address computer by assembler)
 bne $t0, $t1, $as0

beql $t0, $t1, label

 
 lui $as0, 0x0 # (First half of address computed by assembler)  
 lli $as0, 0x0 # (Second half of address computer by assembler)   
 beq $t0, $t1, $as0

sgt $t0, $t1, $t2

 slt $t0, $t2, $t1

Machine Language Specification:

When designing an assembler for the Mach 5 architecture, the translation of assembly language instructions into machine code is straightforward. Each non-pseudo instruction is 16 bits wide. The first 4 bits of this number are the "Operation number" which is specified in the table above. The remaining 14 bits are the parameters, listed in the same order as above.

Example
Assembly Instruction: add $t0, $t1, $t2 Machine Instruction: 1010 0011 0100 0101
Assembly Instruction: lui $t0, 0x23 Machine Instruction: 0011 0011 0010 0011
Assembly Instruction: neg $t0, $t1 Machine Instruction: 0010 0011 0100 0000

Example


 Assembly Instruction:	add	$t0, $t1, $t2
 Machine  Instruction:  1010 0011 0100 0101


 Assembly Instruction:	lui	$t0, 0x23
 Machine  Instruction:  0011 0011 0010 0011


 Assembly Instruction:  neg     $t0, $t1
 Machine  Instruction:  0010 0011 0100 0000

Register Specification:

General Purpose

Register Name	Register Number	Perferred Use
$zero	0	Always contains the value 0. Cannot be changed.
$one	1	Always contains the value 1. Cannot be changed.
$as0	2	Reserved for assembler use
$as1	3	Reserved for assembler use
$as2	4	Reserved for assembler use
$k0	5	Reserved for kernal use
$t0	6	Volitile Storage
$t1	7	Volitile Storage
$t2	8	Volitile Storage
$t3	9	Volitile Storage
$t4	10	Volitile Storage
$t5	11	Volitile Storage
$f0	12	Storage space for arguments and return values from 'function' calls.
$f1	13	Storage space for arguments and return values from 'function' calls.
$f2	14	Storage space for arguments and return values from 'function' calls.
$sp	15	The pointer to the top of the stack.

Special Purpose

Register Name	Register Number	Usage
$disp0	0	Holds the value displayed onto the first LED Display
$disp1	1	Holds the value displayed onto the second LED Display
$disp2	2	Holds the value displayed onto the third LED Display
$disp3	3	Holds the value displayed onto the fourth LED Display
	4	RESERVED
$sw0	5	Holds the values of the switch input
$pc	6	External view of the program counter. (Read-only)
$epc	7	Stores the value of the PC before the last exception occured
$irflag	8	Stores the a value which contains important information about the last interrupt that occured
	9	RESERVED
$s00	10	Storage which is consistent across function calls
$s01	11	Storage which is consistent across function calls
$s02	12	Storage which is consistent across function calls
$s03	13	Storage which is consistent across function calls
$s04	14	Storage which is consistent across function calls
$s05	15	Storage which is consistent across function calls
$s06	16	Storage which is consistent across function calls
$s07	17	Storage which is consistent across function calls
$s08	18	Storage which is consistent across function calls
$s09	19	Storage which is consistent across function calls
$s10	20	Storage which is consistent across function calls
$s11	21	Storage which is consistent across function calls
$s12	22	Storage which is consistent across function calls
$s13	23	Storage which is consistent across function calls
$s14	24	Storage which is consistent across function calls
$s15	25	Storage which is consistent across function calls
$s16	26	Storage which is consistent across function calls
$s17	27	Storage which is consistent across function calls
$s18	28	Storage which is consistent across function calls
$s19	29	Storage which is consistent across function calls
$s20	30	Storage which is consistent across function calls
$s21	31	Storage which is consistent across function calls
$s22	32	Storage which is consistent across function calls

Register Transfer Language Specification

Cycle 0	if(interruptOccured && interruptsEnabled) goto Interrupt Handler RTL
Cycle 1	IR = Mem[PC] PC = PC + 4 SPReg[7] = EPC
Cycle 2	A = Reg[IR[11:8]] B = Reg[IR[7:4]] C = Reg[IR[3:0]] SPReg[6] = PC
Cycle 2	if(IR[15:11] == 0)	if(IR[15:11] == 1)	if(IR[15:11] == 2)	if(IR[15:11] == 3)	if(IR[15:11] == 4)	if(IR[15:11] == 5)	if(IR[15:11] == 6)	if(IR[15:11] == 7)	if(IR[15:11] == 8)	if(IR[15:11] == 9)	if(IR[15:11] == 10)	if(IR[15:11] == 11)	if(IR[15:11] == 12)	if(IR[15:11] == 13)	if(IR[15:11] == 14)	if(IR[15:11] == 15)
Cycle 3	if(A == B)	if(A !=B )	A = 0 - B	B = IR[7:0] <<8	B= IR[7:0]	A = B << SE[IR[3:0]]			Reg[11:8] = 0 if(B < C)	EPC = PC	A = B + C	PC = EPC interruptsEnabled = 1	C = B + SE[IR[3..0]]	C = B + SE[IR[3..0]]	A = B \| C	if(IR[10] == 1)	if(IR[10] == 0)
Cycle 4	PC = C	PC = C	Reg[IR[11:8]] = A	B = B[15:8] \|\| A[7:0]	B = A[15:8] \|\| B[7:0]	Reg[IR[11:8]] = A			Reg[IR[11:8]] = 1	PC = PC + SE[IR[11:0]]	Reg[IR[11:8]] = A		A = Mem[C]	Mem[C] = A	Reg[IR[11:8]] = A	SPReg[IR[5:0]] = A	Reg[IR[11:8]] = SPReg[IR[5:0]]
Cycle 5				Reg[IR[11:8]] = B	Reg[IR[11:8]] = B								Reg[IR[11:8]] = A

Interrupt Handler RTL

Cycle 0.5	EPC = PC PC = Reg[5] SPReg[8] = interruptFlag interruptsEnabled = 0

Interrupt Flag Format

16-bit Flag
3-bit type	7-bit reserved	6-bit value

Type is either 1 (for interrupt) or 2 (for exception).
The reserved value is set to zero.
Value is either the id of the device which caused the interrupt or the exception number.

Assumptions about RTL:

=	is an assignment operator
\|	is a bitwise OR
<	is true iff the left operator is less than the right operator
<<	is a left bit shift
\|\|	is a bitwise concatenation
!=	is a bitwise Not Equal
==	is a bitwise Equal
Value[num1:num2]	are the bits between num1 and num2 (inclusive) in Value
if(condition)	continues execution of the instruction if condition is true
SE[Value]	extends value to a 16-bit number which represents the same value as Value
Mem[Value]	is a location in memory
Reg[Value]	is a specific general purpose register
SPReg[Value]	is a specific special purpose register

RTL Test Plan

Verify that each sequence in the RTL specification completes the associated task from the assmebly specification.
Verify that components exist for every operation which is required of the RTL.
Verify that each cycle contains only operations which can occur concurrently thus minimizing clock cycle length.

Components List

Component	Inputs	Outputs	Control Signals	Notes
Operational Units
Adder	Input1_15:0 Input2_15:0	Output_15:0	SubtractEnable	Adds the two inputs and returns the sum in the output.
Comparator	Input1_15:0 Input2_15:0	Output_0:0		Output is high iff the two Inputs are identical.
LTEngine	Input1_15:0 Input2_15:0	Output_0:0		Output is high iff Input1 is less than Input2 when interpreted as 2's complement integers.
Shifter	Input1_15:0 Input2_15:0	Output_15:0		Bit Shifts Input1 by the amount specified in Input2 (which is interpreted as a 2's complement integer).
Single Word Storage
IR	IRIn_15:0	IROut_15:0	IRWrite	Stores the current instruction.
PC	PCIn_15:0	PCOut_15:0	PCWrite	Stores the value of the next memory address to be executed.
EPC	EPCIn_15:0	EPCOut_15:0	EPCWrite	Stores the value of the next memory address to be execution after completion of exception handling.
A	AIn_15:0	AOut_15:0		Temporary Storage
B	BIn_15:0	BOut_15:0		Temporary Storage
C	CIn_15:0	COut_15:0		Temporary Storage
Sign Extension Units
SE4	Input_3:0	Output_15:0		Takes the 4 bit input and replicates the most significant bit until it is 16 bits long.
SE12	Input_11:0	Output_15:0		Takes the 12 bit input and replicates the most significant bit until it is 16 bits long.
Distant Storage
Reg	ReadReg1_3:0 ReadReg2_3:0 ReadReg3_3:0 WriteReg_3:0 WriteValue_15:0	ReadOut1_15:0 ReadOut2_15:0 ReadOut3_15:0	WriteEnable	Reads the values registers which correspond to the values in the ReadReg registers. Can also write a specified value to the register specified in WriteReg iff the WriteEnable flag is set.
SPReg	ReadReg_3:0 WriteReg_3:0 WriteValue_15:0	ReadValue_15:0	WriteEnable	Read values from special purpose registers. Can also write the value in WriteValue to to the specified special purpose register when the WriteEnable flag is set.
Mem	ReadAddress_15:0 WriteAddress_15:0 WriteValue_15:0	ReadValue_15:0	WriteEnable	Reads the value from the specified address in memory. Can also write the specified value to an address in memory if the WriteEnable flag is set.
Other
Control Unit	Opcode_3:0 ComparatorOutput_0:0 ASPWriteFlag_0:0 LTEngineOutput_0:0	Control Flow		Controls operation flow
Concatenator	Input1_7:0 Input2_7:0	Output_15:0		Takes the 8 bits in Input1 and appends the eight bits in Input2.

Sample Programs:

Euclid's Algorithm binary
Volume of a Rectangular Prism binary