Design Document
This document outlines the design and implementation of the Mach 5 Proccessor Architecture.
The Mach 5 architecture is a 16-bit architecture. Each instruction is fixed width at 16 bits. There are 16 addressable instructions and 16
addressable general purpose registers. There are also 128 special purpose registers, some of these registers are availible for use while others have a predefined purpose.
Assembly Language Specification:
| Operation | Parameter 1 | Parameter 2 | Parameter 3 | Description | Operator Number | Sample Instruction |
|---|
| Mathematical Operations |
| add | destination register | source register | source register | Adds the values in the source registers and stores it in the destination register. | 10 | add $t0, $t1, $t2 |
| sub | destination register | minuend register | subtrahend register | Subtracts the value in the subtrahend value from the minuend register and stores the result in the result register | Pseudo | sub $t0, $t1, $t2 |
| or | destination register | source register | source register | Ors the values in the source registers and stores the result in the destination register | 14 | or $t0, $t1, $t2 |
| ori | destination register | source register | 16 bit immediate value | Ors the value in the source register with the 16 bit immediate value | Pseudo | ori $t1, $t2, 0x16 |
| neg | destination register | source register | N/A | Takes number stored in the source register and stores its 2's-compliment negation in the destination register. | 2 | neg $t0, $1 |
| mult | desination register | source register | source register | Multiplies the values in the source registers and stores the result in the destination register | 6 | mult $t0, $t1, $t2 |
| div | destination register | numerator register | denominator register | Divides the value in the numerator register by the value in the denominator register and stores the result in the destination register (NOTE: this is integer division). | 7 | div $t0, $t1, $t2 |
| Shift Operations |
| sll | destination register | source register | 8 bit immediate | Shifts the source register to the left by the immediate value then stores it in the destination register | 5 | sll $t0, $t1, 0x4 |
| srl | destination register | source register | 8 bit immediate | Shifts the source register to the right by the immediate value then store the value in the destination register. | Pseudo | srl $t0, $t1, 0x4 |
| Register Manipulation/Memory Instructions |
| lui | destination register | 8 bit immediate value | N/A | Loads the specified value into the upper 8 bits of a register without altering any other bits. | 3 | lui $t0, 0x12 |
| lli | destination register | 8 bit immediate value | N/A | Loads the specified value into the lower 8 bits of a register without altering any other bits. | 4 | lli $t0, 0x34 |
| li | destination register | 16 bit immediate value | N/A | Loads the immediate value into the destination register. | Pseudo | li $t0, 0x1234 |
| lw | destination register | address register | 4 bit immediate value | Loads the value at the specified address plus offset from memory into the specified register. | 12 | lw $t0, 0x2($t1) |
| la | destination register | Label | N/A | Load the address of the specified Label into the destination register. | Pseudo | la label |
| sw | source register | address register | 4 bit immediate value | Store the value in the specified register to the specifed address in memory plus offset. | 13 | sw $t0, -0x2($t1) |
| asp | general register | Write Flag | special register | Reads the value from the special purpose register into the general register if the write flag is set to zero or writes the value in the general purpose register into the special purpose register if the write flag is set to one. | 15 | asp $t0, 1 , $disp0 |
| wrasp | general register | special register | N/A | Writes the value in the general purpose register into the specified special purpose register. | Pseudo | wrasp $t0, $disp0 |
| reasp | general register | special register | N/A | Reads the value in the special purpose register into the specified general purpose register. | Pseduo | reasp $t0, $disp0 |
| Branch Instructions |
| j | Label | N/A | N/A | Unconditionally jumps to the specified Label. | Pseudo | j label |
| jsp | Label | N/A | N/A | Increments the stack pointer, stores the next execution address at the top of the stack, and jumps to the specified label. | Pseudo | jsp label |
| rsp | N/A | N/A | N/A | Returns to the value at the top of the stack and decrements the stack pointer | Pseudo | rsp |
| bne | source register | source register | jump register | If the source registers are not equal, then execution moves to the address specified in the jump register | 1 | bne $t0, $t1, $t2 |
| bnel | source register | source register | Label | If the source registers are not equal, jump to the specified label. | Pseudo | ben $t0, $t1, label |
| beq | source register | source register | jump register | If the source registers are equal, then continue execution at the address stored in the jump register | 0 | beq $t0, $t1, $t2 |
| beql | source register | source register | Label | If the source registers are equal, jump to the specified label. | Pseudo | beq $t0, $t1, label |
| Logical Instructions |
| slt | destination register | left source register | right source register | Sets the destination register to 1 if the left source register is less than than the right register or to 0 otherwise. | 8 | slt $t0, $t1, $t2 |
| sgt | destination register | leff source register | right source register | Sets the destination register to 1 if the left source register is greater than then right source register or to 0 otherwise. | Pseudo | sgt $t0, $t1, $t2 |
Notes: All opcodes are represented in machine code as 4-bit numbers. All general registers are represented as 4-bit numbers. Special registers are 7-bits in length. The write flag specified in asp is 1 bit. Unless otherwise specifed, all 'source' and 'destination' registers are general registers.
Pseudo Instruction Implementations
sub $t0, $t1, $t2
neg $as0, $t2
add $t0, $t1, $as0
ori $t0, $t1, 0x00
lui $as0, 0x0 # Lower half of immediate value
lli $as0, 0x0 # Upper half of immediate value
or $t0, $t1, $as0
srl $t0, $t1, 0x1
ssl $t0, $t1, 0x-1
li $t0, 0x12
lui $as0, 0x1
lli $as0, 0x2
or $t0, $as0, $0
la $t0, label
lui $as0, 0x0 # (First half of address computed by compiler)
lli $as0, 0x0 # (Second half of address computed by compiler)
or $t0, $as0, $0
wrasp $t0, $disp0
asp $t0, 0, $disp0
reasp $t0, $disp0
asp $t0, 1, $disp0
jsp label
lui $as0, 0x0 # (First half of address computed by assembler)
lli $as0, 0x0 # (Second half of address computer by assembler)
add $sp, $sp, $1
add $sp, $sp, $1
or $as1, $0, $0
lli $as1, 0x6
add $as1, $pc, $as1
sw $as1, 0($sp)
bne $0, $1, $as0
rsp
neg $as0, $1
add $as0, $as0, $as0
add $sp, $sp, $as0
lw $as0, 2($sp)
bne $0, $1, $as0
j label
lui $as0, 0x0 # (First half of address computed by assembler)
lli $as0, 0x0 # (Second half of address computer by assembler)
bne $0, $1, $as0
bne $t0, $t1, label
lui $as0, 0x0 # (First half of address computed by assembler)
lli $as0, 0x0 # (Second half of address computer by assembler)
bne $t0, $t1, $as0
beq $t0, $t1, label
lui $as0, 0x0 # (First half of address computed by assembler)
lli $as0, 0x0 # (Second half of address computer by assembler)
beq $t0, $t1, $as0
sgt $t0, $t1, $t2
slt $t0, $t2, $t1
Machine Language Specification:
When designing an assembler for the Mach 5 architecture, the translation of assembly language instructions into machine code is straightforward. Each
non-pseudo instruction is 16 bits wide. The first 4 bits of this number are the "Operation number" which is specified in the table above. The
remaining 14 bits are the parameters, listed in the same order as above.
Example
|
|---|
Assembly Instruction: add $t0, $t1, $t2
Machine Instruction: 1010 0011 0100 0101
|
Assembly Instruction: lui $t0, 0x23
Machine Instruction: 0011 0011 0010 0011
|
Assembly Instruction: neg $t0, $t1
Machine Instruction: 0010 0011 0100 0000
|
Register Specification:
General Purpose
| Register Name | Register Number | Perferred Use |
|---|
| $zero | 0 | Always contains the value 0. Cannot be changed. |
| $one | 1 | Always contains the value 1. Cannot be changed. |
| $as0 | 2 | Reserved for assembler use |
| $as1 | 3 | Reserved for assembler use |
| $as2 | 4 | Reserved for assembler use |
| $as3 | 5 | Reserved for assembler use |
| $t0 | 6 | Volitile Storage |
| $t1 | 7 | Volitile Storage |
| $t2 | 8 | Volitile Storage |
| $t3 | 9 | Volitile Storage |
| $t4 | 10 | Volitile Storage |
| $t5 | 11 | Volitile Storage |
| $f0 | 12 | Storage space for arguments and return values from 'function' calls. |
| $f1 | 13 | Storage space for arguments and return values from 'function' calls. |
| $pc | 14 | Holds the address of the next instrcution to be executed |
| $sp | 15 | The pointer to the next operation |
Special Purpose
| Register Name | Register Number | Usage |
|---|
| $disp0 | 0 | Holds the value displayed onto the first LED Display |
| $disp1 | 1 | Holds the value displayed onto the second LED Display |
| $disp2 | 2 | Holds the value displayed onto the third LED Display |
| $disp3 | 3 | Holds the value displayed onto the fourth LED Display |
| | 4 | RESERVED |
| $sw0 | 5 | Holds the values of the switch input |
| | 6 | RESERVED |
| | 7 | RESERVED |
| $s00 | 50 | Storage which is consistent across function calls |
| $s01 | 51 | Storage which is consistent across function calls |
| $s02 | 52 | Storage which is consistent across function calls |
| $s03 | 53 | Storage which is consistent across function calls |
| $s04 | 54 | Storage which is consistent across function calls |
| $s05 | 55 | Storage which is consistent across function calls |
| $s06 | 56 | Storage which is consistent across function calls |
| $s07 | 57 | Storage which is consistent across function calls |
| $s08 | 58 | Storage which is consistent across function calls |
| $s09 | 59 | Storage which is consistent across function calls |
| $s10 | 60 | Storage which is consistent across function calls |
| $s11 | 61 | Storage which is consistent across function calls |
| $s12 | 62 | Storage which is consistent across function calls |
| $s13 | 63 | Storage which is consistent across function calls |
| $s14 | 64 | Storage which is consistent across function calls |
| $s15 | 65 | Storage which is consistent across function calls |
| $s16 | 66 | Storage which is consistent across function calls |
| $s17 | 67 | Storage which is consistent across function calls |
| $s18 | 68 | Storage which is consistent across function calls |
| $s19 | 69 | Storage which is consistent across function calls |
| $s20 | 70 | Storage which is consistent across function calls |
| $s21 | 71 | Storage which is consistent across function calls |
| $s22 | 72 | Storage which is consistent across function calls |
| $s23 | 73 | Storage which is consistent across function calls |
| $s24 | 74 | Storage which is consistent across function calls |
| $s25 | 75 | Storage which is consistent across function calls |
| $s26 | 76 | Storage which is consistent across function calls |
| $s27 | 77 | Storage which is consistent across function calls |
| $s28 | 78 | Storage which is consistent across function calls |
| $s29 | 79 | Storage which is consistent across function calls |
| $s30 | 80 | Storage which is consistent across function calls |
Sample Programs:
Euclid's Algorithm binary
Volume of a Rectangular Prism binary